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| Name: |
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Soha Hassoun |
| Title: |
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Assistant Professor of Computer Science
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| Departmental Affiliation: |
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Computer Science Department
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| Degrees: |
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Ph.D., University of Washington;
M.S., Massachusetts Institute of Technology;
B.S.E.E., South Dakota State University |
| Expertise: |
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Computer-aided Design for Integrated Circuits
VLSI and Processor Architectures
High-performance Circuit Design
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| E-mail: |
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soha@cs.tufts.edu
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| Other websites: |
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http://www.cs.tufts.edu/~soha/
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| Scholarship & Research: |
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Hassoun, S., Alpert, C., Thiagarajan, M., "Optimal Buffered Routing Path Constructions for Single and Multiple Clock Domain Systems", International Conference on Computer-Aided Design (ICCAD), November 2002.
Hassoun, S., Cromer, C., Eduardo Calvillo-G'amez, "Verifying Clock Schedules in the Presence of Cross Talk", Design Automation and Test in Europe (DATE) Conference, March 2002.
Kudlugi, M., Hassoun S., Selvidge, C., and Pryor, D., "A Transaction-Based Unified Simulation/Emulation Architecture for Functional Verification", Design Automation Conference (DAC), June, 2001.
Hassoun, S. "Critical Path Analysis Using a Dynamically Bounded Delay Model", Design Automation Conference (DAC), June, 2000.
Hassoun, S., and McCreary, C. "Regularity Extraction Via Clan-Based Structural Circuit Decomposition", International Conference on Computer-Aided Design (ICCAD), Nov., 1999.
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